// module name: ram
// author: yangtao2019
// date: 2021.07.12

`timescale 1ns / 1ps

// default capacity: 4KB-2^12-128*32bits-128*4Bytes
module ram
#(
    parameter ADDR_LEN = 7,
    parameter CAPACITY = (2<<ADDR_LEN)*32
)
(
    input clk,
    input read,
    input write,
    input [ADDR_LEN-1:0] addr,
    output [63:0] read_data,
    input[63:0] write_data,
    input DoubleWd
);
    
    parameter n = (2<<ADDR_LEN);

    // regs
    reg [31:0] regs[n-1:0];
    //initial $readmemh("D:/Vivado_project/oscpu01/oscpu01.srcs/data/data_mem_test0.txt", regs);
    
    // write operation 
    always @ (posedge clk) begin
        if (write) begin
            if (DoubleWd)   // Double word operation
                {regs[(addr<<2)+1], regs[addr<<2]} <= write_data;
            else            // Word operation
                regs[addr<<2] <= write_data[31:0];
        end
    end

    // read operation
    assign read_data = {64{read}} & {regs[(addr<<2)+1], regs[addr<<2]};

endmodule